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Microinstruction With Next Address Field



The control memory is used to store the microinstructions in groups. Here each group is used to specify a routine. The control memory of each computer has the instructions which contain their micro-programs routine. These micro-programs are used to generate the micro-operations that will be used to execute the instructions. Suppose the address sequencing of control memory is controlled by the hardware. In that case, that hardware must be capable to branch from one routine to another routine and also able to apply sequencing of microinstructions within a routine. When we try to execute a single instruction of computer, the control must undergo the following steps:




Microinstruction With Next Address Field



We are able to transform the bits of instruction code into an address with the help of control memory where routine is located. This process can be called the mapping process. The control memory required the capabilities of address sequencing, which is described as follows:


In the above diagram, we can see a block diagram of a control memory and associative hardware, which is required for selecting the address of next microinstruction. The microinstruction is used to contain a set of bits in the control memory. With the help of some bits, we are able to start the micro-operations in a computer register. The remaining bits of microinstruction are used to specify the method by which we are able to obtain the next address.


In this diagram, we can also see that the control address register are able to recover their address with the help of four different directions. The CAR is incremented with the help of incrementer and then chooses the next instruction. The branching address will be determined in the multiple fields of microinstruction so that they can provide results in branching.


If there are status bits of microinstruction and we want to apply conditions on them, in this case, we can use conditional branching. An external address can be shared with the help of a mapping logic circuit. The return address will be saved by a special register. This saved address will be helpful when the micro-program requires returning from the subroutine. At that time, it requires the value from the unique register.


If these status bits come together with the microinstruction field, they are able to control the decision of a conditional branch, which is generated in the branch logic. Here the microinstruction field is going to specify a branch address. The multiplexer is used to implement the branch logic hardware. If the condition is met, it will be branch to the initial address. Otherwise, it will increment the address register.


If we load the branch address into the control address register from the control memory, we are able to implement the unconditional branch microinstruction. If the condition is true, it will go to the branch, which is referred to as the address from the next address field of the current microinstruction. Otherwise, it will fall through. There are various types of conditions that need to be tested: Z(zero), C(carry), O(overflow), N(negative), etc.


With the help of this process, a micro-program will be provided to each computer instruction. The micro-program contains the capacity of four microinstructions. If less than four microinstructions are used by the routine, the location of unused memory can be used for other routines. If more than four microinstructions are used by the routine, it will use the addresses 1000000 through 1111111.


Subroutines can be referred to as programs that are used to accomplish a particular task by the other routines. With the help of employing subroutines, we can save the microinstructions. These subroutines use the common sections of microcode, such as effective address computation. The main routine is able to get the address for the return with the help of a subroutine register. In another word, we can say that it becomes a source to transfer the address to a main routine. The register file is used to store the addresses for subroutines. These register files can be structured in a way that the register will be organized in the 'Last in first out' (LIFO) stack.


The microinstructions can be determined by symbols. It is interpreted to its binary format with an assembler. The symbols should be represented for each field in the microinstruction. The users should be enabled to represent their symbolic addresses. Each line in an assembly language represents symbolic instruction. These instructions are divided into five fields such as label, micro-operations, CD, BR, and AD.


A micro-program sequencer attached to a control memory inputs certain bits of the microinstruction, from which it determines the next address for control memory. A typical sequencer provides the following address-sequencing capabilities:


Two-address approach is simple but it requires more bits in the microinstruction. With a simpler approach, we can have a single address field in the micro instruction with the following options for the next address.


The address selection signals determine which option is selected. This approach reduces the number of address field to one. In most cases (in case of sequential execution) the address field will not be used. Thus the microinstruction encoding does not efficiently utilize the entire microinstruction.


In this approach, there are two entirely different microinstruction formats. One bit designates which format is being used. In this first format, the remaining bits are used to activate control signals. In the second format, some bits drive the branch logic module, and the remaining bits provide the address. With the first format, the next address is either the next sequential address or an address derived from the instruction register. With the second format, either a conditional or unconditional branch is specified.


As shown in the table, each microinstruction can have only three micro-operations, one from each field. If it uses less than three, it will result in more than one operation using the no operation binary code.


As shown in the table, when condition 00 is connected with BR (branch) field, it results in an unconditional branch operation. Then the execution is read from memory the indirect bit I is accessible from bit 15 of DR. The status of the next bit is supported by the AC sign bit. If all the bits in AC are 1, then it is indicated as Z (its binary variable whose value is 1). The symbols U, I, S, and Z can indicate status bits while writing microprograms.


The BR (branch) field includes 2 bits. It can be used by connecting with the AD (address) field. The reason for connecting with the AD field is to select the address for the next microinstruction. The table illustrates the various branch fields and their functions.


As shown in the table, when BR = 00, a JMP operation is implemented and when BR = 01, a subroutine is called. The only difference between the two instructions is that when the microinstruction is saved, the return address is saved in the Subroutine Register (SBR).


These two operations are dependent on the CD field values. When the status bit condition of the CD field is defined as 1, the address that is next in order is transferred to CAR. Else, it gets incremented. If the instruction needs to return from the subroutine, its BR field is determined as 10.


This results in the transfer of the return address from SBR to CAR. The opcode bits of instruction can be mapped with an address for CAR if the BR field is 11. They are present in DR (11 - 14) after instruction is read from memory. The last two conditions in the BR fields are not dependent on the CD and AD field values.


The microinstructions stored in the control memory of a processor have a width of $26$ bits. Each microinstruction is divided into three fields: a micro-operation field of $13$ bits, a next address field $(X),$ and a MUX select field $(Y).$ There are $8$ status bits in the input of the MUX.


A microinstruction is a bit pattern in which each bit (or combination of bits) drives the control signals of the hardware. A microprogram is a series of microinstructions that accomplishes some specific task. On this web page we will look at some very simple microprograms. We will assume that every microprogram begins at address 0x000 in the control store. A microprogram doesn't terminate unless the computer is turned off. For the sake of simplicity, however, we will assume that there is a "halt" microinstruction. This instruction is all zeroes except the 8 low-order bits of the next address field.


The trick here is to understand how the JMPN bit affects the program. When the JMPN bit and the N flag are both 1, the high order bit of the MPC will be 1 otherwise the high-order bit is determined by the value in the next address field. Since this is a two-way branch, it follows that the address in the next address field must have a high-order bit of 0. Otherwise, the high-order bit would already be one and it wouldn't matter what the values of the JMPN and N bits were. As a general rule, when a conditional jump is executed, the high-order bit of the next address must be zero and represents the address of the next instruction if the jump fails. If the jump succeeds, the high-order bit will be set to 1 to form the address of the next instruction when the jump succeeds.


Usually the addresses are generated by some combination of a counter, a field from a microinstruction, and some subset of the instruction register. A counter is used for the typical case, that the next microinstruction is the one to execute. A field from the microinstruction is used for jumps, or other logic. 041b061a72


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